YY-Electron Wireless Home Security Alarm System Bedienungsanleitung PDF herunterladen (Seite 2)

Special Issue of International Journal of Computer Applications (0975 – 8887)

International Conference on Electronic Design and Signal Processing (ICEDSP) 2012

ATmega16 has 16 KB programmable flash memory and static

RAM of 1 KB.

The AVR core combines a rich instruction set with 32 general

purpose working registers. All the 32 registers are directly

connected to the Arithmetic Logic Unit (ALU), allowing two

independent registers to be accessed in one single instruction

executed in one clock cycle. The resulting architecture is more

code efficient while achieving throughputs up to ten times

faster than conventional CISC microcontrollers

PIN DESCRIPTIONS

VCC : Digital supply voltage

GND : Ground

Port A (PA7.PA0): Port A serves as the analog inputs to the

A/D Converter.

Port A also serves as an 8-bit bi-directional I/O port, if the

A/D Converter is not used. Port pins can provide internal pull-

up resistors (selected for each bit). The Port A output buffers

have symmetrical drive characteristics with both high sink and

source capability. When pins PA0 to PA7 are used as inputs

and are externally pulled low, they will source current if the

internal pull-up resistors are activated. The Port A pins are tri-

stated when a reset condition becomes active, even if the

clock is not running.

Port B (PB7..PB0): Port B is an 8-bit bi-directional I/O port

with internal pull-up resistors (selected for each bit). The Port

B output buffers have symmetrical drive characteristics with

both high sink and source capability. As inputs, Port B pins

that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a

reset condition becomes active, even if the clock is not

running.

Port C (PC7..PC0): Port C is an 8-bit bi-directional I/O port

with internal pull-up resistors (selected for each bit). The Port

C output buffers have symmetrical drive characteristics with

both high sink and source capability. As inputs, Port C pins

that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a

reset condition becomes active, even if the clock is not

running. If the JTAG interface is enabled, the pull-up resistors

on pins

PC5 (TDI), PC3 (TMS) and PC2 (TCK) will be activated

even if a reset occurs.

Port D (PD7..PD0): Port D is an 8-bit bi-directional I/O port

with internal pull-up resistors (selected for each bit). The Port

D output buffers have symmetrical drive characteristics with

both high sink and source capability. As inputs, Port D pins

that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a

reset condition becomes active, even if the clock is not

running.

RESET: Reset Input. A low level on this pin for longer than

the minimum pulse length will generate a reset, even if the

clock is not running. Shorter pulses might not generate a reset.

XTAL1: Input to the inverting Oscillator amplifier and input

to the internal clock operating circuit.

XTAL2: Output from the inverting Oscillator amplifier.

AVCC: AVCC is the supply voltage pin for Port A and the

A/D Converter. It should be externally connected to VCC,

even if the ADC is not used. If the ADC is used, it should be

connected to VCC through a low-pass filter.

AREF: AREF is the analog reference pin for the A/D

Converter

TABLE 1 - ADMUX REGISTER

REF

ADL

Bit 7:6 – REFS1:0: Reference Selection Bits: These bits select

the voltage reference for the ADC. If these bits are changed

during a conversion, the change will not go in effect until this

conversion is complete (ADIF in ADCSRA is set). The

internal voltage reference options may not be used if an

external reference voltage is being applied to the AREF pin.

TABLE 2 - VRS

REFS1

REFS0

Voltage Refrence Selection

Aref,Internal Vref Turned Off

Avcc With External Capacitor

Reserved

Internal 2.56 Voltage Ref With

External Capacitor At Ref Pin

Bit 5 – ADLAR: ADC Left Adjust Result: The ADLAR bit

affects the presentation of the ADC conversion result in the

ADC Data Register. Write one to ADLAR to left adjust the

result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately,

regardless of any ongoing conversions.

Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits:

The value of these bits selects which combination of analog

inputs are connected to the ADC .These bits also select the

gain for the differential channels. If these bits are changed

during a conversion, the change will not go in effect until this

conversion is complete (ADIF in ADCSRA is set).The

Combinations are as follows:-

TABLE 3 -MUX ADC COMBINATIONS

MUX 4..0

ADC SELECTED

00000

ADC0

00001

ADC1

00010

ADC2

00011

ADC3

00100

ADC4

00101

ADC5

00110

ADC6

00111

ADC7

TABLE 4 - ADCSRA

ADA

ADP

1 2 3 4

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